The present invention relates to matrix-addressed liquid crystal display devices.
Recently there has been vigorous development of high density matrix-addressed liquid crystal display devices which have a large number of image elements used for image display. Such liquid crystal devices frequently make use of thin film transistor (TFT) arrays formed by the use of thin film integrated circuit technology on one side of a substrate.
FIG. 7 shows an example of the arrangement of a single picture element of a matrix-addressed liquid crystal display device. In this figure, a signal line X connected to the drain electrode D of a TFT 1 and an address line Y connected to the gate electrode G of the TFT 1 are arranged in an orthogonal relationship to allow for column and row scanning of elements. The source electrode S of the TFT 1 is connected to one end of the capacity C.sub.GS between the gate and display electrodes. The liquid crystal element is turned on due to the buildup of the capacity C.sub.LC of the liquid crystal cell responsive to the gate electrode of the TFT 1 and the source electrode combined with the display electrode. In a matrix-addressed display device with drive switching elements each consisting of an an amorphous Si thin film transistor, each of the capacities inherently provided in respective liquid crystal cells which constitute pixels only stores the charge and holds a signal potential during one scanning period. Therefore, since connecting discrete capacitors to such cells is unnecessary, the area on the substrate occupied by discrete capacitors results in reduction of the effective useful area as compared to the area not contributing to the picture element on the substrate.
On the other hand, the capacity C.sub.GS between the gate and source electrodes cannot be disregarded because the signal-hold capacity is reduced.
FIG. 8 is a waveform diagram which explains the drive signals for the image element shown in FIG. 7. In (a) of this figure, the solid line waveform represents the scanning signal voltage V.sub.Y supplied to the address line Y and the dotted line waveform represents the display signal voltage V.sub.X supplied to the signal line X. Further, (b) in the same figure represents the signal voltage V.sub.S which is held by charging the liquid crystal cell capacity C.sub.LC. As shown in FIG. 8(a), the scanning signal voltage V.sub.Y has a frame scanning period T.sub.F. Further, as 8(a) shows, the polarity of display signal voltage V.sub.X is inverted during every frame scanning period T.sub.F using the polarity inversion reference potential V.sub.B as the datum. When a scanning signal voltage V.sub.Y and a display signal voltage V.sub.X is supplied respectively to the address line Y and the signal line X, the liquid crystal cell voltage with the waveform shown in FIG. 8(b) is held in the liquid crystal capacity C.sub.LC, giving rise to the level shift dV between the desired voltage entered and the holding voltage. Since the level shift dV is superimposed on the signal voltage Vs, a difference in voltage magnitude between positive and negative polarities is produced and the voltage alternately applied to each of the liquid crystal cell will be different. In other words, a DC component is introduced to the signal voltage Vs.
In more detail, the cell voltage drops below the desired reference voltage Vs by the level shift dV, at one voltage polarity and when the polarity is reversed, the cell voltage drops by the level shift dV below the reference voltage Vs.
A method disclosed in Japanese Patent Application Laid-open No. 59-119328 is provided to equalize the different voltages applied to the cell. By the method, the drain voltage of a thin film transistor is biased at a constant voltage corresponding to the level shift dV for compensating the dV component contained in the cell voltage. Alternatively, the level shift dV is compensated by applying a bias voltage equal to the left shift dV to the common electrode of the liquid crystal cell. However the level shift is not effectively compensated for by such a method.
The level shift dV is produced due to the existence of the capacity C.sub.GS between the gate and display electrodes and is give by the equation ##EQU1## taking V.sub.G as the amplitude of the scanning signal voltage V.sub.Y. Hence, assuming d for the cell gap, A is the display electrode area, e.sub.LC is the dielectric constant of the liquid crystal material and e.sub.O is the vacuum dielectric constant, the liquid crystal capacity C.sub.LC can be given as ##EQU2##
Since the dielectric constant for the liquid crystal material e.sub.LC changes with the orientation of the liquid crystal molecules representative to the applied voltage V.sub.S, the capacitance can be given as a function of the applied voltage V.sub.S in the form EQU C.sub.LC =K.sub.1 .multidot.f(V.sub.S).
Consequently, the level shift dV also will be a function of the applied voltage V.sub.S and can be given as EQU dV=K.sub.2 .multidot.f(V.sub.S).
K.sub.1 and K.sub.2 are constants. It is known, that in such image displays, the level shift dV will also assume different values when different values are adopted for the effective voltage applied to the liquid crystal cell.
FIG. 9 is a diagram for explaining this behaviour, the vertical axis V shows the display signal voltage V.sub.X and the value V.sub.S of the voltage applied to the liquid crystal cell. The solid lines OP and ON give the amplitudes of the display signal voltage V.sub.X extending from the black to the white level and has been shown as a straight line for the sake of convenience. Furthermore, the horizontal line V.sub.B passing through the point O shows the polarity inversion reference potential for the display signal. Where there is no level shift dV, the solid OP or ON projected onto the vertical axis is the voltage V.sub.S applied to the liquid crystal cell. The opposite common electrode potential of the liquid crystal cell in this case is the polarity inversion reference potential V.sub.B.
But in practice, since there is a level shift dV in the case of twisted nematic (TN) type liquid crystal cells with parallel arranged polarizing filter to the nematic molecules, the points P and N corresponding to the white level shift respectively to points P.sub.1 and N.sub.1 and the point O corresponding to the black level shifts to point O.sub.1. The fact that the size of the level shift dV.sub.BL of the point O corresponding to the black level is greater than the size of the level shift dV.sub.WH at points P and N corresponding to the white level is due to the fact that the dielectric constant of the liquid crystals is small. Thus the liquid crystal molecules are in a state close to perpendicular to the direction of the electric field and therefore the liquid crystal cell capacity C.sub.LC is small compared with points P or N corresponding to the white level. Consequently, if the point O.sub.1 is set to the opposite common electrode potential V.sub.C of the liquid crystal cell, the voltage V.sub.S applied to the liquid crystal cell will have different values on the positive side and negative side (polarity inversion side) with respect to the opposite common electrode potential V.sub.C even though the display signal voltage has the same amplitude for positive and negative with respect to the polarity, inversion reference potential V.sub.B. The effect of this is that a direct current is applied to the liquid crystal which is undesirable for the life of the liquid crystal and produces a flicker in the display because the fundamental frequency of the voltage V.sub.S applied to the liquid crystal cell is halved. Furthermore, when the opposite common electrode potential V.sub.C is increased above the condition shown in FIG. 9, a point is reached at which the flicker disappears, but at this condition tonal rendering in the display is lost and the ideal AC drive condition is not produced.
Even though the bias voltage corresponding to dV.sub.WH is applied to the source electrode or the drain electrode as described in the aforementioned No. 59-119328, it results in the characteristic similar to V.sub.s shown by the dotted line in FIG. 9, so and has the same problem as described above.